Digital electronic circuits require clock signals in order that data sent from and received by the circuits may be processed in a specific sequence for correct recovery. In general, such clock signals are generated using crystal oscillator (XO) circuits.
These XO circuits, which may also include temperature compensation functionality, are notionally large circuits comprising, amongst other things, a number of elements including capacitors, resistors, inductors and transistors. These elements occupy a large area.
Under certain conditions, the inclusion of such a notionally large XO circuit in a circuit will be undesirable, particularly in circumstances where space is at a premium. In addition, the relatively large power requirements of such circuits make them undesirable in situations where there are power constraints such as in mobile devices for example.
A further problem arises in that the frequency of a clock signal generated using a clock circuit must be synchronized with the frequency of an incoming data stream in order that data may be correctly recovered. This is generally accomplished by oversampling the incoming data stream and using some form of digital signal processing to determine the samples which best represent the actual data.
Alternatively, the synchronization of the clock and incoming data frequencies may be effected using a phase-locked loop arrangement, wherein the difference in frequency between the input signal and a variable frequency oscillator providing a variable frequency clock signal provides a control signal operable to facilitate synchronization of the frequencies.
Both synchronization arrangements require significant space for implementation on a digital integrated circuit (IC), and have relatively high power requirements, which may be undesirable in situations where area and power are limited.